7 segments · 81 companies · as of Sep 18, 2026
EDA & Silicon IP
Design tools and reusable circuit building blocks behind AI chips
Where it sits
Fed by: Chip ManufacturingFeeds: Servers & Systems
EDA software implements and verifies chip designs, while silicon IP supplies reusable CPUs, neural engines, memory interfaces and interconnect. Hardware emulators let developers validate complex processors before fabrication. Together these tools and blocks determine whether AI architectures become working silicon.
Why now
Larger chiplet systems raise verification and interface demands. Ansys, Artisan and ARC have changed owners, AI agents are entering design workflows, and Chinese vendors are expanding domestic tools after the temporary 2025 US EDA export restrictions were lifted.
Chip Design & Simulation
Design implementation, circuit simulation and physical signoff turn a chip architecture into manufacturable silicon. AI processors need these tools to close timing, power, thermal and signal-integrity constraints across increasingly complex dies.
Fusion Compiler and PrimeTime implement and sign off AI chips; acquired Ansys adds thermal and multiphysics analysis
leaderGenus, Innovus and Spectre cover implementation and circuit analysis; acquired Hexagon D&E expands multiphysics
leaderCalibre physical signoff, Aprisa implementation and Altair simulation support advanced compute-chip design
majorPathWave ADS, acquired PowerArtist RTL power analysis and optical-design tools support mixed-signal compute designs
nicheVictory TCAD, SmartSpice and Gateway model devices and analog circuits used in compute-chip and interface development
nicheAether design environment, ALPS simulation and Argus physical verification support domestic Chinese IC development
challengerNanoSpice circuit simulation and model-characterization software support analog/mixed-signal design and foundry PDKs
nicheGigaDesigner, Asca and SX-Meister serve analog layout and physical verification, with limited direct AI-chip exposure
nicheIRIS, Metis and Hermes 3D simulate electromagnetic behavior and chiplet-system interconnect before tape-out
nicheTCMagic and ATCompiler automate test-chip physical design; SmtCell tools characterize foundation-cell libraries
major3DIC Designer and NodeClosure implement multi-die and advanced-node chip designs alongside its verification tools
challengerMATLAB and Simulink model chip algorithms; HDL Coder translates hardware models into synthesizable RTL
majorRocSyn synthesis, Aguda physical implementation and ChimeTime timing signoff cover the digital ASIC design flow
challengerEasylogicECO modifies synthesized netlists to implement functional changes without rerunning the entire ASIC flow
nicheReinforcement-learning layout tools implement analog circuits, including SerDes blocks, against physical design constraints
emerging
Sources: trendforce.com, mathworks.com, giga-da.com, easylogiceda.com, astrus.ai, investor.synopsys.com
Verification & Prototyping
Simulation, formal verification and hardware emulation expose logic errors before tape-out. Dedicated emulators and FPGA prototypes let AI-chip teams validate large designs and bring up software while their final silicon is still being built.
Palladium Z3 emulation and Protium X3 FPGA prototyping validate large AI SoCs before fabrication
leaderZeBu Server 5, ZeBu-200 and HAPS-200 combine emulation and prototyping; VCS, Verdi and VC Formal verify RTL
leaderVeloce Strato CS uses Crystal emulation chips; Primo CS and proFPGA CS prototype designs on AMD FPGAs
majorVersal Premium VP1902 supplies the programmable silicon inside Veloce CS and new HAPS/ZeBu-200 prototypes
majorStratix 10 and Agilex FPGAs serve as configurable silicon inside third-party ASIC prototyping systems
majorProdigy S8 uses Versal Premium FPGAs; Logic Matrix and S7 systems support large SoC prototypes
challengerGalaxSim and GalaxFV software combine with HuaPro FPGA prototypes and HuaEmu hardware emulation
challengerDigital verification tools and September-launched Verification GOAT agents automate chip validation workflows
challengerHES-DVM and HES FPGA boards support hybrid emulation, co-simulation and physical SoC prototyping
nicheHDL Verifier cosimulates RTL against MATLAB/Simulink reference models and generates SystemVerilog UVM testbenches
nicheProprietary verification CLI generates UVM testbenches and runs pipeline checks for complete NPU and sensor-fusion SoCs
niche
Sources: mathworks.com, silverchips.co.kr, news.synopsys.com, cadence.com, news.siemens.com, s2cinc.com
CPU & Configurable Compute IP
Licensable processor cores and embedded programmable logic let custom-chip designers add control and general compute without building every architecture themselves. The segment covers CPU IP, DSPs and genuine eFPGA IP, including FPGA-targeted soft cores.
Cortex and Neoverse CPU cores plus Compute Subsystems underpin mobile, embedded and AI-server custom silicon
leaderPerformance P870-D and embedded RISC-V cores license processor architecture for customer AI and host SoCs
majorAX and NX RISC-V cores, Andes Custom Extension and vector support license configurable CPU compute
majorTensilica Xtensa configurable processors and HiFi/Vision DSPs provide control, audio and signal-processing IP
majorMIPS and the June-acquired ARC Classic, ARC-V and VPX DSP portfolio license processor IP beyond foundry services
challengerSensPro and audio DSP IP add programmable signal processing and sensor fusion to customer inference SoCs
majorAscalon X/S RISC-V cores and coherent compute IP license host and control processors for custom AI designs
challengerT-Head XuanTie C920/C950 RISC-V core families license customizable general compute alongside its captive cloud chips
challengerConfigurable 100/1000/5000-series RISC-V IP spans embedded controllers through multithreaded application processors
emergingN/UX-series RISC-V cores span embedded control to Linux-capable application processing and coherent clusters
challengerDubhe-100 licenses server-class RISC-V CPU architecture; earlier core IP also serves embedded SoCs
challengerAtrevido CPU IP combines custom RISC-V execution with wide vectors and memory-latency handling
nicheCHERI-secure cores and Studio CPU customization remain central after its announced low-end RISC-V divestiture
nicheAustralis generates custom eFPGA hard IP so ASIC designers can integrate reprogrammable logic
majorSpeedcore embeds FPGA logic, DSP and machine-learning processor blocks inside customer ASICs
majorStandard-cell eFPGA Soft IP and Hard IP provide process-portable programmable logic within custom SoCs
nicheKVX/MPPA many-core compute IP and custom-chip services extend Coolidge processing into customer designs
nichePropel RISC-V MC soft CPU IP adds RV32IMCE control to Lattice FPGAs; this is FPGA IP rather than merchant ASIC CPU IP
nicheAcquired Videantis v-MP6000UDX processor IP unifies DSP, image processing and video workloads on programmable cores
nicheSTAR-MC2 Cortex-M52-derived CPU IP adds Helium vector compute; STAR platforms combine it with licensed Ethos NPUs
challengerAzurite and Linux-capable Calcite RISC-V IP add configurable control and application CPUs to customer SoCs
emergingBMR bare-metal and SCL Linux RISC-V soft-core families license processor compute for FPGA-based customer designs
nicheDevelops RISC-V-based DFP processor IP for configurable automotive and industrial dataflow computation
emergingAI Foundry releases ET-SoC-1 RISC-V minion-core RTL and vector/tensor extensions under Apache 2.0 licensing
emerging
Sources: semiwiki.com, incoresemi.com, bluespec.com, armchina.com, aifoundry.org, gf.com
Neural & Graphics Compute IP
Licensable NPU, GPU, vector and vision-processing blocks integrated inside customer AI chips. Compiler support, supported models, memory efficiency and proven integration determine which architectures win designs.
Ethos-U85 NPU IP scales to transformer-capable edge inference alongside Cortex CPU cores
leaderNeo NPU, NeuroEdge AI co-processor and Tensilica Vision DSPs use the NeuroWeave software platform
majorNeuPro-M and NeuPro-Nano license neural compute from high-performance inference to always-on embedded ML
majorVivante VIP9000 and Pico NPU families provide programmable inference for vision, wearables and automotive SoCs
majorE-Series GPU IP integrates neural compute for edge AI; IMGNN libraries support GPU-based inference
majorENLIGHT Pro combines transformer-capable NPU IP with RISC-V vector processing for camera and automotive inference
challengerCMNP video NPU IP accelerates super-resolution, noise reduction and image recognition beside codec blocks
nicheTensix compute IP licenses programmable AI cores for customer accelerators and automotive inference chips
challengerChimera programmable GPNPU IP runs C++ kernels and neural workloads across 1-864 TOPS configurations
challengerOrigin Evolution NPU IP maps edge and data-center inference onto a configurable packet-based architecture
challengerAkida and Akida GenAI IP license event-based inference, temporal models and state-space neural processing
nicheZIA AI processor IP provides configurable image-inference engines for compact Japanese edge-device designs
nicheThe acquired ARC NPX NPU portfolio extends MIPS by GF beyond CPU/DSP cores into licensable neural processing
challengerAndes vector cores and custom instruction extensions provide programmable neural compute in customer AI SoCs
challengerAll-in-One IP combines Atrevido CPU, vector and tensor units for configurable AI inference processors
nicheIntelligence X-series vector processor IP couples programmable RISC-V compute to customer neural accelerators
challengerLicenses Blackwell GPU and DLA compute IP into MediaTek Dimensity AX C-X1 automotive cockpit silicon
nicheLicenses Radeon RDNA graphics/compute IP to Samsung Exynos; Xclipse in Exynos Auto V920 uses RDNA 2
nicheOwned Videantis v-MP6000UDX IP executes neural inference and classical vision alongside its analog-compute platform
nicheZhouyi X3 and X3-Pro NPU IP target CNN, transformer and agent inference; licensable blocks are distinct from Arm's Ethos
challengerDFP inference IP development targets embedded vehicle and factory workloads; it is an IP program, not a merchant ADAS SoC
emerging
Sources: armchina.com, denso.com, arm.com, cadence.com, ceva-ip.com, verisilicon.com
Interface & Chiplet IP
Licensable interfaces, on-chip networks, memory controllers and mixed-signal blocks connect compute dies and feed accelerators. These placements describe IP inside silicon, excluding standalone network switches, retimers, cables and optical modules.
DesignWare PCIe, CXL, UCIe and high-speed SerDes controller/PHY IP connect custom AI processors and compute chiplets
leaderPCIe/CXL, UCIe and high-speed SerDes IP connect compute dies and reusable subsystems in heterogeneous AI SoCs
leaderAcquired Alphawave licenses high-speed SerDes, UCIe and controller IP, with custom connectivity chiplets
majorPCIe/CXL controller and security IP protect and connect custom compute; former PHY assets belong to Cadence
majorGLink-2.5D/3D and UCIe die-to-die interface IP connect custom compute chiplets in multi-die AI accelerators
majorFlexNoC and Ncore on-chip networks connect CPUs, neural engines and memory with coherent and noncoherent fabrics
major28G-224G SerDes IP and OmniConnect AXI-over-VSR chiplets connect customer compute dies; Weaver adds LPDDR5X interfaces
majorPCIe, USB and MIPI interface IP supplies high-speed physical connections inside customer compute and edge SoCs
majorOIC interconnect IP coordinates transfers between CPUs, NPUs and memory subsystems in customer AI SoCs
challengerUSB, PCIe and other interface IP connects custom compute SoCs alongside its ASIC design-service platforms
majorNuLink die-to-die PHY and NuGear chiplets connect compute and memory across standard or advanced substrates
challengerInnolink UCIe and high-speed SerDes IP provide chip-to-chip links for custom AI processors and chiplets
challengerPLL, clocking and SerDes mixed-signal IP supplies timing and physical interfaces inside advanced compute SoCs
nicheOwned Analog Bits supplies PLL, SerDes and process/voltage/temperature sensing IP for custom chip designs
nicheAcquired Blue Cheetah's BlueLynx BoW/UCIe PHY and link-layer IP connects AI and RISC-V chiplets
challengerNVLink Fusion opens coherent CPU/XPU attachment to partner custom silicon through its licensed interconnect ecosystem
leaderUCIe, PCIe Gen5, HBM3/E and 32G multi-protocol SerDes IP connect compute dies and memory in domestic AI SoCs
challengerMIPI C/D-PHY IP is licensed by Ambarella for edge-AI chips; high-speed SerDes expands its interface portfolio
nicheWeaveIP provides coherent and noncoherent network-on-chip fabric spanning CPU, accelerator, memory and chiplet interfaces
challengerGlasswing licenses CNRZ-5 short-reach SerDes for in-package chiplet links; Tigerwing addresses faster chip-to-chip links
nicheUCIe IP contributes die-to-die connectivity to the Egis/Alcor Arm Neoverse CSS chiplet collaboration
emerging
Sources: design-reuse.com, bayasystems.com, kandou.ai, prnewswire.com, credosemi.com, rambus.com
Memory & Foundation IP
Memory controllers, PHYs, embedded-memory compilers, standard cells and analog monitoring blocks turn compute architectures into manufacturable chips. These licensed building blocks feed and stabilize AI arithmetic; they are distinct from selling DRAM or fabrication capacity.
DesignWare HBM and DDR controller/PHY IP implements high-bandwidth memory access in AI accelerators
leaderArtisan standard cells and memory compilers join DDR/HBM PHY IP to supply the physical building blocks of custom chips
leaderHBM and DDR memory-controller IP manages accelerator memory transfers; DDR/HBM PHY ownership moved to Cadence
majorHBM4 controller and PHY IP provide reusable memory subsystems inside customer AI ASICs and multi-die accelerators
majorOMC controllers and ORBIT memory PHYs feed customer NPUs and CPUs, forming its licensed total-memory subsystem
challengerSRAM, register-file and ROM compilers plus standard-cell libraries supply process-qualified embedded storage and logic
majorNeoFuse embedded nonvolatile-memory IP and NeoPUF security primitives add on-chip storage and hardware identity
leaderSRAM/register-file/ROM compilers and multi-threshold standard-cell libraries implement embedded compute foundations
majorV.Libs supplies process-specific standard cells, I/O cells and memory compilers within its SiPaaS design platform
majorEmbedded SRAM, register-file and ROM compilers supply production IP, including GF 22FDX single-port SRAM
nicheYOU DDR3/4 and LPDDR3/4 Combo controller/PHY IP is silicon-proven on 28HKD and reusable through YouSiP platforms
nicheHBM4/3E, GDDR7 and LPDDR6 controller/PHY IP supplies memory access blocks for custom AI and graphics processors
challengerOwned Analog Bits licenses PLL, clocking and process/voltage/temperature sensing IP for customer ASIC foundations
nicheRing/LC PLL, oscillator and timing IP supplies low-jitter clocks inside advanced compute-chip designs
majorAeonic digital clocking and power-management IP adapts on-chip frequency and voltage for efficient compute operation
challengerEmbedded telemetry-agent IP measures timing, power and aging inside silicon to support lifetime compute-chip monitoring
majorSamsung-process SRAM, NVM, standard-cell and I/O libraries are customized through its Foundation IP and CLS services
niche
Sources: coressol.com, cadence.com, verisilicon.com, silvaco.com, m31tech.com, britesemi.com
AI-Assisted Chip Design
AI models and agents help engineers explore floorplans, optimize RTL and generate or debug verification workloads. Incumbent EDA vendors integrate these methods into signoff flows while startups build tools that must prove accuracy on real customer designs.
DSO.ai and VSO.ai optimize design and verification; AgentEngineer introduces autonomous workflows under customer evaluation
leaderCerebrus and ChipStack AI agents optimize design and verification; Millennium M2000 accelerates multiphysics simulation
leaderQuesta One adds AI verification and property generation; Aprisa AI applies learning to RTL-to-GDS implementation
majorDeepMind AlphaChip uses reinforcement learning for chip floorplanning, with disclosed deployments in TPU and Axion designs
majorDevelops AI models for physical design and verification as the first phase of an intended workload-to-GDS chip-design service
emergingAgentic RTL design and verification tools report deployments at MediaTek, Micron and over 120 semiconductor companies
challengerArtificial Chip Intelligence models combine physics-informed training with semiconductor design and optimization
emergingNormal EDA uses customer design data for RTL generation, formal verification and AI-assisted silicon co-design
challengerPreqorsor predicts RTL power, performance and area; its copilot finds and repairs functional design bugs
emergingVerification GOAT AI agents, introduced in September, assist domestic chip verification workflows
emergingAI agents use reinforcement learning to generate analog layouts and optimize design-rule, area and circuit constraints
emergingEasyAI ECO applies learning engines to synthesis, DFT and place-and-route change orders; demonstrated at DAC 2026
nicheNEX agents coordinate architecture, RTL, verification and physical-design tasks across commercial and open EDA tools
emergingEagleWision applies AI to RTL generation, verification, bug repair and layout optimization within silicon design services
nicheAgentic Silverchips CLI automates UVM generation and verification pipelines for custom RISC-V and NPU designs
niche
Sources: astrus.ai, semiwiki.com, businesswire.com, wipro.com, siemens.com, nvidianews.nvidia.com
Glossary
- EDA
- Electronic design automation: software used to design, simulate, verify and implement integrated circuits.
- Silicon IP
- A reusable licensed circuit design incorporated into another company's chip, rather than a finished chip.
- RTL
- Register-transfer-level code describes digital logic before synthesis into gates and physical implementation.
- Emulation
- Specialized hardware runs a model of a chip before fabrication to check function and develop software.
- PHY
- The physical interface circuitry that turns digital data into electrical signals across a link.
- NoC
- Network on chip: an internal fabric connecting processor cores, accelerators, memory and interfaces.
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