7 segments · 69 companies · as of Sep 18, 2026
Custom AI Silicon
Workload-specific chips and the designers that bring them to production
Where it sits
Fed by: Chip ManufacturingFeeds: Servers & Systems
Custom AI silicon matches hardware to a particular model, cloud fleet or autonomy stack. Hyperscalers and labs own the requirements, while specialist partners provide implementation and reusable IP. The map separates chip programs from foundry capacity and system assembly.
Why now
OpenAI has disclosed Jalapeno, Google has split its next TPU generation into training and inference variants, and Marvell has added a Google custom-silicon agreement. Chiplets broaden design options while Korean and Taiwanese partners win more advanced-node work.
Custom Compute Partners
Merchant designers translate hyperscaler or model-specific requirements into production compute silicon. They supply architecture, physical implementation and integration rather than simply selling standard GPUs.
Co-designs Google TPUs, Meta MTIA and OpenAI Jalapeno; Anthropic orders TPU racks through its Google partnership
leaderAWS custom-silicon partner; July Google agreement explicitly adds inference accelerators and near-memory compute
majorCustom XPU service adopts Nvidia's NVLink Fusion chiplet under the August agreement; a specific Google TPU socket is unconfirmed
challengerAcquired Alphawave's custom silicon, SerDes and chiplet capabilities complement Oryon CPU and Hexagon NPU designs
challengerImplements d-Matrix's Corsair on TSMC N6 through production; additional hyperscaler sockets are not assumed
majorCustom AI ASIC implementation combines GLink die-to-die connectivity with silicon-proven HBM controller and PHY IP
challengerA14 CPU/xPU compute-chiplet platform targets September 2026 tape-out to validate future custom AI SoC designs
challengerDevelops custom NVLink-enabled Xeon with Nvidia; Central Engineering provides external ASIC design capabilities
challengerCo-designs a Meta-specific MI450-family GPU for the first tranche of Meta's up-to-6GW agreement
majorAGI CPU is its first production silicon product, co-developed with Meta for AI infrastructure orchestration
emergingHardcore Models platform turns customer neural models into specialized silicon; HC1 demonstrates hardwired Llama inference
emergingSamsung 5nm HPC design platform turns Rebellions ATOM and other customer AI architectures into implemented silicon
challengerADP620 Neoverse CPU platform and REBEL integration supply a design route for customer AI compute on Samsung 2nm
challengerDeepX DX-M2 implementation pairs customer NPU architecture with Samsung 2nm design services; prototypes target 2027
nicheNeoverse CSS reference platforms and FPGA-Go-ASIC services implement customer host and accelerator SoCs
nicheSiPaaS integrates Vivante neural compute, memory and image-processing IP into customer AI ASICs
challengerMobius100 CSS V3 emulation and edge-NPU design platforms support customer Arm CPU and AI accelerator ASICs
emerging
Sources: marketsandmarkets.com, nvidianews.nvidia.com, alcormicro.com, openai.com, investor.marvell.com, mediatek.com
Global ASIC Design Houses
Design houses turn customer RTL and selected IP into tapeouts and supplied chips. Advanced-node implementation, verified reusable blocks and the ability to manage production distinguish these partners.
Implements large AI ASICs and chiplets; d-Matrix identifies it as the Corsair N6 production design partner
leaderCombines custom ASIC implementation with in-house GLink, UCIe and HBM4 IP for multi-die AI designs
majorSolution SoC engagements cover customer architecture through implementation, including Arm-based AI compute chiplets
majorNeoverse CSS integration and FPGA-Go-ASIC services convert customer compute designs into custom SoCs
challengerOne-stop AI-ISP chip design combines NPU, image-processing and LPDDR IP; a smartphone customer's chip is in production
majorYouSiP reference platforms and YOU DDR/LPDDR IP support specification-to-chip implementation of custom AI SoCs
challengerCustom ASIC/LSI designs integrate proteanTecs monitoring under a September 2026 collaboration for advanced compute
nicheSankalp-backed engineering designs custom AI accelerators, NPUs and RISC-V cores from RTL through physical implementation
nicheDream Chip adds AI and automotive SoC architecture to its RTL, verification and physical-design services
nicheFormer Sondrel supplies high-performance AI and automotive ASIC architecture, implementation and full-lifecycle delivery
nicheeInfochips supplies custom ASIC architecture, RTL, verification and physical design through turnkey silicon engagements
nicheTurnkey Silicon Device service covers custom ASIC development through production with foundry and assembly partners
nicheASIC turnkey service covers specification, IP integration, implementation and production management for customer chips
challengerIsrael ASIC center implements customer chips from architecture and RTL through verification, layout and production
nicheSilicon engineering covers architecture, RTL and GDSII implementation plus wafer and assembly coordination for ASICs
nicheTurnkey ASIC service takes mixed-signal and digital designs from specification through qualification and volume supply
nicheFull-Stack ASIC services combine front-end design, physical implementation and production management for AI SoCs
niche
Sources: einfochips.com, wipro.com, cyientsemi.com, ltts.com, capgemini.com, ensilica.com
Korean ASIC Design Partners
Korean design partners connect domestic AI chip startups and overseas customers to qualified ASIC implementation. Samsung DSP and TSMC VCA relationships define distinct design routes, without counting wafer fabrication here.
5nm HPC platform implements Rebellions ATOM; Open-Silicon and Analog Bits extend turnkey design and reusable IP
leaderADP620 integrates Neoverse CSS V3 CPU chiplets with REBEL under a Samsung 2nm platform collaboration
majorImplements DeepX DX-M2 on Samsung 2nm; the current prototype target is H1 2027 after an earlier 2026 schedule
majorTSMC VCA design partner implements BrainChip's second-generation AKD2500 under a February 2026 supply contract
challengerVia CoAsia SEMI co-develops REBEL-based heterogeneous chiplets and I/O integration, targeting validation by end-2026
challengerADEON ASIC platform and Samsung design services cover logic, DFT, physical implementation and production support
challengerQuantaline subsidiary delivers AI and automotive SoCs from specification and RTL through tape-out and production
challengerSamsung SAFE VDP supplies logic, DFT and signoff; disclosed work includes TSMC 6nm NPU hardening and AI Neoverse SoCs
nicheSamsung SAFE VDP supplies RTL-to-GDSII design and full-SoC verification for NPU, RISC-V and sensor-fusion chips
nicheSamsung SAFE VDP provides logic, DFT and place-and-route services; chip design is separate from its EDA resale work
niche
Sources: semiconductor.samsung.com, alphachips.co.kr, asdtglobal.com, silverchips.co.kr, quantaline.com, noveldesign.co.kr
Hyperscaler AI Chips
Cloud and internet groups design accelerators around internal models, recommendation systems and serving fleets. Silicon stays with the parent company even when external design partners or customers are involved.
Ironwood TPU is generally available; TPU 8t targets training and TPU 8i targets post-training and inference
leaderAnnapurna's Trainium3 is shipping; Trainium4 remains a future generation rather than confirmed 2026 broad availability
majorMaia 200 uses FP4/FP8 tensor cores and 216GB HBM3e for GPT models, Microsoft Foundry and Copilot inference
majorMTIA 300 handles recommendation training; MTIA 400 expands workloads and 450/500 target 2027 generative inference
majorT-Head's Zhenwu M890 follows 810E with native FP4-through-FP32 compute and the SAIL software stack
majorAscend 950PR targets prefill and recommendation; 950DT is scheduled for Q4 2026 training and decode
majorControlled Kunlunxin designs the announced M100 inference chip for 2026 and M300 training-inference successor for 2027
challengerZixiao is its disclosed cloud-AI inference program; newer generations and current deployment volumes remain unverified
nicheReuters-reported SeedChip and Samsung manufacturing talks were disputed by ByteDance; no working chip is confirmed
emerging
Sources: cloud.google.com, aboutamazon.com, blogs.microsoft.com, ai.meta.com, alibabagroup.com, huawei.com
Lab & Enterprise Chip Programs
Model labs and enterprise-platform owners design chips for their own workloads or software stack. This includes confirmed silicon and clearly labelled development efforts, but not ordinary purchases of third-party GPUs.
Jalapeno inference chip is co-designed with Broadcom; June engineering samples precede planned end-2026 deployment
leaderPrivate Cloud Compute runs on custom Apple silicon co-designed with its secure cloud inference stack
majorTelum II's on-chip inference and PCIe Spyre accelerator are co-designed around enterprise models and IBM Z workloads
majorConfirmed an internal chip-design team for Claude workloads in August; no finished proprietary accelerator has been disclosed
emergingMN-Core 2 and the developing L1000 align proprietary AI software with purpose-built training and inference chips
nicheReported Izanagi AI-chip program remains unconfirmed as a product; Graphcore funding does not establish a shipped successor
emerging
Sources: security.apple.com, reuters.com, openai.com, ibm.com, preferred.jp, group.softbank
Automaker-Designed AI Chips
Automakers increasingly design the processors that run perception and driving models. The placements cover silicon ownership and development, not vehicle sales, autonomy software alone or general automotive power chips.
AI4 is deployed and AI5 has taped out; AI6 and renewed Dojo3 development remain future compute programs
leaderShenji NX9031 runs in NIO and Onvo models; NX9031U expands the chip family's target into embodied AI
challengerTuring AI processors run proprietary driving models and the IRON robot's onboard inference stack
challengerMach M100 is a 5nm in-house AI SoC, deployed as a dual-chip configuration in the L9 Livis
challengerXuanji A3 4nm driving SoC was announced as mass-produced in May; named vehicle rollout timing remains unverified
challengerRAP1 is its in-house autonomy processor with RivLink interconnect, announced for the next ACM3 compute platform
emerging
Sources: reuters.com, xpeng.com, cnevpost.com, electrek.co, techinsights.com
Compute Chiplet Platforms
Reusable CPU, accelerator and interconnect dies let customers assemble custom compute chips. Only chiplet design and licensed integration roles are included; fabrication, packaging services and standalone switches remain elsewhere.
NVLink Fusion provides a reusable chiplet and design foundation connecting customer XPUs to its compute ecosystem
leaderXDSiP compute design integrates face-to-face 2nm silicon; Fujitsu identifies it as an enabler for MONAKA
majorCustom XPU design, die-to-die links and NVLink Fusion support heterogeneous compute-chip integration
majorAugust Nvidia agreement adopts the NVLink Fusion chiplet as a prevalidated foundation for customer XPUs
majorAlphawave's reusable connectivity chiplets and custom silicon extend Oryon/Hexagon-based compute designs
challengerNVLink Fusion design services and advanced-node ASIC implementation connect customer accelerators to Nvidia GPUs
majorGLink-3D, UCIe and HBM4 controller/PHY blocks enable custom multi-die AI accelerators
majorDevelops an A14 multi-core CPU/xPU validation chiplet; September 2026 tape-out is planned, not confirmed production
challengerNeoverse CSS supplies CPU subsystems for custom chiplets, including ADTechnology's REBEL-linked platform
majorCo-develops custom Xeon processors with NVLink to couple x86 host compute to Nvidia GPUs
challengerTensix AI and Ascalon CPU IP combine with acquired Blue Cheetah die-to-die IP for custom compute chiplets
challengerREBEL chiplets and UCIe-Advanced links underpin REBEL-Quad and its ADTechnology/CoAsia development programs
challengerADP620 CPU-chiplet design joins Neoverse CSS V3 to REBEL accelerators in a co-developed 2nm platform
challengerCustom connectivity chiplets extend Scorpio/Sunrise integration into XPU packages; the program is in development
emergingNVLink Fusion implementation and verification solutions help customers integrate licensed links into custom XPU designs
majorNVLink Fusion design infrastructure and reusable IP support customer XPU chiplets and heterogeneous compute integration
majorAnnapurna plans NVLink Fusion integration for Trainium4 custom accelerators; this remains a future generation
majorNVLink Fusion custom-silicon partnership supports CPU/XPU design integration; no specific customer chip is assigned
emergingMONAKA CPU participates in NVLink Fusion for future coherent coupling of its Arm host compute to Nvidia GPUs
emergingJanuary NVLink Fusion partnership develops RISC-V host integration with Nvidia accelerators; customer silicon is future work
emergingNuLink die-to-die PHYs enable multi-die AI compute over organic substrates, with UCIe and BoW integration options
challengerWeaveIP and WeaverPro unify coherent chiplet fabrics; Openchip selected them for RISC-V AI compute systems
challengerFlexNoC and Ncore fabric IP plus Magillem integration tools connect heterogeneous compute blocks across chiplet designs
nicheGlasswing CNRZ-5 die-to-die IP links compute dies inside multi-chip modules using standard organic packaging
niche
Sources: eliyan.com, bayasystems.com, arteris.com, kandou.ai, nvidianews.nvidia.com, investors.broadcom.com
Glossary
- ASIC
- An application-specific integrated circuit designed for a defined workload rather than general-purpose use.
- RTL
- Register-transfer-level code describes a digital circuit before its logic is mapped into physical silicon.
- Turnkey
- A design engagement that can cover implementation, tapeout and delivery of finished chips to the customer.
- Chiplet
- A separately designed silicon die combined with other dies to create a larger processor or system chip.
- Tapeout
- The release of final chip design data for manufacturing; it does not by itself mean volume production.
Heat, spend, exposure and shares are editorial estimates. How to read the map ↗