7 segments · 54 companies · as of Sep 18, 2026
CPUs & Infrastructure Processors
Host processors and programmable offload chips that keep AI compute working
Where it sits
Fed by: Chip ManufacturingFeeds: Servers & Systems
AI servers still need CPUs to run applications, prepare inputs and control accelerators. DPUs move infrastructure work into dedicated programmable processors. x86 remains central while custom Arm CPUs and emerging RISC-V designs broaden the host-side supply chain.
Why now
Agentic workloads increase demand for host compute as Venice, Clearwater Forest, Vera and Graviton5 arrive. Arm has entered merchant silicon, while BlueField-4 and Salina expand offload. MONAKA and several RISC-V CPUs remain dated roadmaps rather than established volume supply.
x86 & Enterprise CPUs
Server CPUs run operating systems, prepare data and orchestrate accelerators. This segment includes established x86 suppliers and explicitly different Power, mainframe and LoongArch enterprise architectures.
Xeon 6 and 18A-based Xeon 6+ Clearwater Forest host AI workloads; Diamond Rapids remains a later roadmap generation
leaderEPYC 9005 Turin hosts current GPU fleets; Zen 6 EPYC 9006 Venice brings 2nm compute and PCIe Gen6
leaderC86 x86 server CPUs provide domestic hosts for Chinese AI systems alongside its separate DCU accelerators
majorPower11 and Telum II serve enterprise hosts; Telum II integrates inference and I/O offload into the mainframe CPU
nicheKaiSheng KH-50000 uses x86-compatible chiplets with up to 96 cores for domestic cloud and AI inference servers
challengerJintide Gen6 P-core CPUs combine Intel-sourced x86 cores with proprietary security pre-check and dynamic checking
nicheLoongArch 3C6000/S, /D and /Q processors scale from 16 to 64 cores for Chinese servers; they are not x86 chips
niche
Sources: tomshardware.com, amd.com, intel.com, newsroom.ibm.com, zhaoxin.com, hkexnews.hk
Arm Server Silicon
Merchant Arm CPUs and their silicon partners compete on core density, memory bandwidth and CPU-to-accelerator integration. Several 2026 announcements are future products and are labelled with their expected availability.
Grace and 88-core Vera host AI systems; Vera connects coherently to Rubin and reached initial customers in 2026
leaderAGI CPU enters merchant server silicon with Meta as lead co-developer and early systems available
challengerWholly owned Ampere supplies AmpereOne and AmpereOne M, with up to 192 custom Arm cores
majorMONAKA combines 2nm compute and 5nm cache/I/O dies; standalone CPU sales are announced for November 2026
challengerKunpeng 920 supplies Arm-compatible hosts; the announced Kunpeng 950 and TaiShan 950 extend its AI-server roadmap
majorDragonfly C1000 uses Oryon server cores and a 250-plus-core chiplet design; commercial availability targets 2028
emergingRhea1 uses 80 Neoverse V1 cores for European HPC; general availability is targeted for late 2026
emergingTengyun S2500 integrates 64 FTC663 Arm-compatible cores and supports coherent multi-socket servers
nicheCustom 2nm face-to-face compute SoC implementation supports Fujitsu's MONAKA server-CPU program
nicheMobius100 Neoverse CSS V3 CPU platform is demonstrated in emulation for AI/HPC chiplets; production silicon is unconfirmed
emerging
Sources: aijourn.com, blogs.nvidia.com, newsroom.arm.com, amperecomputing.com, global.fujitsu, qualcomm.com
Cloud-Designed Host CPUs
Cloud operators design host CPUs to optimize their own software fleets and the CPU work surrounding AI accelerators. Programs range from deployed Arm instances to newly announced or reported internal architectures.
Graviton5 powers generally available M9g/C9g instances, pairing its Arm CPU with sixth-generation Nitro
leaderGoogle Axion's Neoverse V2 CPUs power C4A instances while Titanium handles infrastructure offloads
majorCobalt 200 Arm-based VMs entered early access preview in June 2026, with Azure Boost offloading I/O
majorYitian 710 Armv9 processors power ECS instances under Shenlong, with 128-core host compute
majorCo-developed Arm AGI CPU to orchestrate its AI fleet alongside MTIA, rather than merely buying a standard CPU
emergingPrivate Cloud Compute nodes use custom Apple silicon to host secure cloud-side Apple Intelligence inference
nicheReuters reports internal Arm and RISC-V server-CPU development; no completed design or commercial shipment is confirmed
emerging
Sources: aws.amazon.com, cloud.google.com, azure.microsoft.com, alibabacloud.com, newsroom.arm.com, reuters.com
Programmable DPU Silicon
DPUs combine programmable processors with data-path acceleration to move virtualization, storage and security work off host CPUs. FPGA implementations and embedded DPU cores are included when the underlying processor role is explicit.
BlueField-3 and Grace-based BlueField-4 run DOCA infrastructure services; BF4 adds 64 Arm cores and 800G I/O
leaderPensando Salina uses a P4-programmable pipeline for virtualization, security, storage and KV-cache data movement
majorE2100/E2200 IPU families isolate cloud infrastructure processing from tenant CPUs; FPGA IPUs support custom offload
majorOCTEON 10 combines Neoverse N2 cores, programmable packet processing and security/storage acceleration
majorE1 is an 800G programmable DPU for infrastructure offload; it is distinct from the company's X2 switch
challengerFPGA-based network and storage DPUs offload AI server infrastructure through its programmable DPU software stack
challengerT7 programmable DPU silicon is in evaluation; the company schedules DPU production availability for December 2026
emergingCoolidge v2 MPPA processors expose programmable KVX cores for storage, networking and AI data-path offload
nicheAgilex FPGAs provide the programmable datapath silicon inside Intel/Napatech F2070X-class DPU implementations
majorTelum II integrates a low-latency DPU for mainframe I/O acceleration alongside its enterprise CPU and AI engine
nicheF2070X DPU combines Agilex FPGA and Xeon D with proprietary Link-Programmable network and infrastructure offload
challengerAcquired DreamBig's MARS chiplet DPU platform and networking IP in July 2026 to extend programmable infrastructure compute
emerging
Sources: napatech.com, sec.gov, static1.squarespace.com, resources.nvidia.com, amd.com, intel.com
Cloud & Regional Offload Chips
Internal cloud offload chips and independent regional DPU designers implement isolation and data movement below the host OS. Named processors are mapped separately from switches, conventional NICs and finished server appliances.
Nitro processors offload VPC, EBS, local storage and security, with sixth-generation Nitro paired to Graviton5
leaderTitanium custom microcontrollers and IPU-based offloads remove networking, storage and security work from host CPUs
majorAzure Boost custom hardware and the acquired Fungible DPU team offload virtualization, networking and remote storage
majorCIPU acts as the Apsara infrastructure service processor, accelerating virtualized compute, storage and networking
majorK2-Pro uses the proprietary KPU architecture to combine network, storage, security and compute offload
challengerSunrise 400G DPU silicon supplies Tencent's Xuanling program; a ChiNext filing is not a completed IPO
challengerD1205CQ DPU exposes dual 100GbE ports for programmable cloud network and storage offload
emergingNFP processors and Agilio firmware execute programmable packet and infrastructure offload; FX adds Arm host cores
nicheTaihang DPU implements proprietary vQPE, BOE and BDR engines in FPGA logic to offload virtualized network and storage I/O
niche
Sources: cloud.baidu.com, nebula-matrix.com, jaguarmicro.com, aws.amazon.com, cloud.google.com, learn.microsoft.com
RISC-V Host Architectures
Licensable cores and developing CPU architectures aim to make RISC-V useful for server control, AI orchestration and host processing. Ecosystem readiness and working silicon matter more than projected benchmark claims.
P870-D targets data-center CPUs; BigSky prototypes and ROCm collaboration advance RISC-V AI-host software
leaderTT-Ascalon X and June-launched Ascalon S license high-performance and dense RISC-V host cores
challengerAX66 out-of-order CPU IP targets advanced RISC-V compute; Condor server-core IP returned after that unit closed
majorMarch-launched XuanTie C950 licenses customizable RISC-V host compute for agentic AI alongside Arm-based Yitian
challengerConfigurable 5000/5100 RISC-V cores offer out-of-order execution and multithreading for data-center customers
emergingAcquired Ventana's Veyron V1/V2 RISC-V server-core technology and team; no standalone Veyron shipment is confirmed
emergingUX1000/UX1060 Linux-capable out-of-order cores support RVA23 and coherent clusters for host and network compute
challengerAugust-launched Dubhe-100 server CPU IP supports RVA23 and scalable coherent clusters; customer chips are in development
emergingAtrevido RISC-V CPU IP and Gazzillion Misses memory handling target AI hosts and data-intensive server designs
emergingCHERI-enabled application cores and Studio customization tools underpin its post-pivot secure processor roadmap
nicheDevelops a new RISC-V host CPU microarchitecture for AI data centers; no production release date is committed
emerging
Sources: qualcomm.com, eetimes.com, sifive.com, tenstorrent.com, akeana.com, nucleisys.com
Emerging Host Platforms
New server and accelerator-host platforms combine alternative instruction sets with memory and I/O designs. These projects range from available developer silicon to preproduction CPUs and custom design reference platforms.
Rhea1 Arm server CPU is in bring-up for late-2026 availability, aimed at European exascale CPU workloads
challengerArbel RISC-V CPU is being productized as a Maverick host; 64/128-core production processors target Q1 2028
emergingSG2044 combines 64 XuanTie C920v2 cores and RVV 1.0 for Linux workstations and server-class HPC experiments
nicheK3 RVA23 AI CPU and X100 cores support Linux developer and smaller host platforms, below hyperscale-server maturity
emergingRISC-V AI/HPC SoCs and BER10 development pair with SUSE software enablement for European compute platforms
emergingThunderbird I's RISC-V manycore accelerator is demonstrated with E4; delisted InspireSemi remains a private specialist
emergingADP620 Neoverse V3 CPU-chiplet reference platform supports custom hosts attached to REBEL AI accelerators
emerging64-core Neoverse CSS evaluation-platform design on Intel 18A supports customer server ASIC development
emergingEight-core CSS V3 emulation platform validates Mobius100 host designs before custom CPU-chiplet fabrication
emergingEIC7702X pairs SiFive P550 CPU clusters with neural compute for RISC-V developer hosts, below hyperscale-server class
emergingP1 powers Arm Linux developer boards such as Orion O6; host CPU, GPU and NPU share memory in a client-class SoC
emerging
Sources: eswincomputing.com, developer.cixtech.com, inspiresemi.com, nextsilicon.com, sipearl.com, alphaxiv.org
Glossary
- Host CPU
- The processor that runs the operating system and coordinates applications, data movement and accelerators.
- DPU
- A data processing unit offloads programmable networking, storage, security and virtualization from host CPUs.
- IPU
- Infrastructure processing unit: Intel and cloud vendors use this name for programmable infrastructure offload.
- RISC-V
- An open instruction-set standard; individual processor implementations can still be proprietary licensed IP.
- Coherency
- Rules that keep shared memory views consistent across CPU cores or cooperating processors.
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