7 segments · 97 companies · as of Sep 18, 2026
Edge AI Silicon
Processors that run inference in local devices, vehicles and sensors
Where it sits
Fed by: Chip ManufacturingFeeds: Servers & Systems
Edge AI silicon executes models close to users and sensors, avoiding a cloud round trip for every decision. The supply chain includes client NPUs, embedded vision SoCs, discrete accelerators, automotive compute, programmable logic and low-power neural controllers. This theme maps chips and IP, not finished devices.
Why now
New client generations bring stronger local models, while Jetson Thor, embedded NPUs and neural MCUs broaden deployment. A20 Pro, Tensor G6 and Dimensity 9600 Pro update the 2026 client picture. Kinara has moved to NXP, while Hailo, Alif and Silicon Labs have pending acquisition agreements.
Phone & PC AI Processors
Application processors integrate CPU, GPU and neural compute to run models locally in phones and PCs. These placements map the chip designs themselves, with announced generations distinguished from products already available by the September cutoff.
A20 Pro debuts with September 18 availability; M5-family Neural Engines and GPU neural accelerators serve local AI
leaderSnapdragon 8 Elite Gen 5 and X2 Elite use Hexagon NPUs; the next mobile generation is still a later-September launch
leaderSeptember-launched Dimensity 9600 Pro adds NPU 1090; co-designed GB10/N1X extends its CPU work into local AI PCs
majorRyzen AI 400 and AI Max PRO 400 combine XDNA 2 NPUs with Radeon graphics and unified memory for local inference
majorCore Ultra Series 3 Panther Lake brings an 18A compute tile, NPU and Xe3 graphics to AI PCs and embedded clients
majorExynos 2600 integrates CPU, NPU and Xclipse graphics on 2nm GAA; Exynos 2700 remains a development program
majorGoogle Tensor G6 adds a larger on-device TPU and runs Gemini Nano in August-launched Pixel 11 hardware
majorGB10 combines Blackwell GPU and MediaTek-co-designed Arm CPU; N1X extends the design into announced Windows PCs
challengerSeptember-announced Kirin 9050 Pro integrates HiSilicon CPU, GPU and NPU designs for handset inference
majorXRING O3 enters mass production after its August launch, extending the in-house smartphone SoC program beyond O1
challengerT9300 uses heterogeneous CPU/GPU compute and an AI SDK for imaging and on-device models; a dedicated NPU is not assumed
nicheLumex CSS licenses C1 CPU and Mali G1 client subsystems with SME2 AI acceleration; it is IP for customer processors
majorP1 integrates twelve Arm CPU cores, Immortalis graphics and a 30-TOPS NPU for PCs and compact local-AI systems
challengerK3 combines X100 RISC-V CPUs and A100 AI cores for client hardware, supporting local language-model execution
emerging
Sources: arm.com, developer.cixtech.com, cdn-resource.spacemit.com, koreatimes.co.kr, tomshardware.com, apple.com
Embedded & Vision SoCs
Embedded application and camera processors combine local inference with image processing, video and control. The category also includes cockpit and camera-domain SoCs whose main role is application or vision processing rather than centralized driving decisions.
CV7 and CV5/CV2-family CVflow processors integrate neural inference, ISP and video encoding for edge cameras
leaderi.MX 95 combines application cores, vision processing and eIQ Neutron NPU for industrial and embedded inference
majorRZ/V2H and RZ/V2N use DRP-AI accelerators for embedded vision, robotics and real-time industrial processing
majorAM62A and AM67A integrate vision pipelines and neural acceleration; AM67A adds a 4-TOPS engine and multi-camera ISP
majorDragonwing IQ8/IQ9 integrate Hexagon inference, camera processing and real-time control for industrial edge systems
majorGenio Pro and Genio 720/520 combine application CPUs with NPUs for embedded vision and local generative AI
majorCore Ultra Series 3 edge variants combine CPU, GPU and NPU processing for industrial vision and local inference
majorRK3588 and RK3576 integrate NPUs and multimedia engines for embedded vision, industrial control and small edge computers
majorT527 and T536 integrate 2-TOPS NPUs with Arm CPUs and industrial interfaces for local vision and control
challengerA123X and C305X2 sample with transformer-capable ADLA3 NPUs; mass production is scheduled for Q4 2026
challengerAX650 and AX8850 combine vision pipelines and NPUs; AX8850 supports 18 INT8 TOPS or 72 INT4 TOPS
challengerAstra SL2610 Linux/Android SoCs combine Cortex-A55/M52 cores with transformer-capable NPUs
challengerNT98539A integrates HW-CNN Gen3 neural processing and AI ISP; distributor reference designs document local camera inference
nicheAmeba Pro 3 integrates dual NPUs and AI ISP; Ameba Pro 2 serves lower-power connected vision applications
nicheSSD268G and SSC-series vision SoCs integrate proprietary IPU neural compute with camera and video processing
majorDolphin5 design integrates Cortex-A76/A55, Mali-G78AE and Ethos-N78 IP for automotive cockpit inference
challengerAPACHE5/6 combine camera ISP, Arm CPUs and neural acceleration for ADAS vision and driver monitoring
nicheSE1000 cockpit SoC integrates CPU, graphics and neural processing for local voice, vision and automotive interfaces
challengerX9 and X10 cockpit SoCs combine application compute with NPUs; X10 targets local multimodal language models
challengerEIC7700-family SoCs integrate SiFive RISC-V hosts, NPUs and graphics for local vision and AI application systems
emergingOAX4600 combines Cortex-A53 CPUs, RGB-IR ISP, stacked DDR3 and a 2-TOPS NPU for driver and occupant monitoring
nicheTX5368 combines reconfigurable ISP, RNE neural compute and video codecs for embedded vision and transformer inference
challenger
Sources: ovt.com, tsingmicro.com, eswincomputing.com, ambarella.com, nxp.com, renesas.com
Embedded AI Accelerators
Discrete NPUs, integrated AI processors and compact compute chips execute inference in industrial, robotic and local edge systems. They compete on usable models, software, memory and power; future silicon is explicitly separated from production products.
Jetson Orin and Thor T5000 silicon runs vision-language-action and multimodal inference using CUDA/TensorRT
leaderRyzen AI Embedded P100/X100 combines Zen 5, Radeon and XDNA 2 compute in long-life industrial AI processors
majorAcquired Kinara Ara-1/Ara240 discrete NPUs offload vision and generative inference from i.MX host processors
majorDiscrete Hailo-8 handles vision, Hailo-10H adds local generative AI, and Hailo-15 integrates camera processing
majorModalix MLSoC integrates Arm compute and machine-learning acceleration for embedded multimodal and language models
challengerThe 1600 GSP streams inference graphs in Pathfinder/Xplorer products; GSP2 remains a later roadmap
challengerMetis digital in-memory inference chips serve edge vision; Europa adds vector cores and larger-model support
challengerKL730 combines vision and a reconfigurable NPU; KL1140 adds Mamba and language-model execution at the edge
challengerDX-M1 is in mass-produced edge modules; 2nm DX-M2 remains under development with 2027 prototypes now reported
challengerARIES discrete NPUs and REGULUS 10-TOPS SoCs target multi-camera vision, drones and compact local inference
challengerSAKURA-II accelerator and MERA compiler execute CNN and transformer inference under embedded power constraints
challengerMX3 is in production for local inference; MX3+ is in design and MX4 production is targeted for 2028
challengerEN100 analog in-memory accelerator targets local AI PCs and edge systems through an early-access program
emergingM1 analog processing units execute inference in flash arrays; acquired Videantis adds automotive processor technology
challengerBM1688/CV186AH tensor-processing SoCs combine embedded host compute, vision and SOPHON SDK neural inference
nicheRK1820/RK1828 AI co-processors accelerate local language and vision-language models, including cascaded deployments
challengerOCTEON 10 integrates an ML inference engine beside Neoverse N2 cores for real-time network-edge analytics
nicheEagle-N chiplet uses Tenstorrent NPU cores for automotive and robotic inference; production targets 2027
emergingZ1 thermodynamic chip targets low-power edge sampling in an M.2 design; early access is planned for 2027
emergingControlled Chengheng unit launched CH37 edge-AI SoCs in August 2026 for local neural inference
emergingSPU-001 sparse neural coprocessor integrates 1MB SRAM and an SPI host interface for low-power audio and sensor inference
niche
Sources: jingjiamicro.com, femto.ai, nvidia.com, nxp.com, sima.ai, hailo.ai
Automotive AI Compute
Automotive compute chips execute perception, driver assistance and increasingly combined cockpit workloads under safety and thermal constraints. Merchant suppliers compete with in-house automaker processors; future chip programs are not counted as current production wins.
DRIVE Orin and production-grade DRIVE Thor supply GPU/DLA compute for vehicle perception and driving models
leaderSnapdragon Ride Elite combines Oryon, Adreno and Hexagon; dual SA8797P powers Leapmotor's integrated controller
majorEyeQ6H executes perception and sensor fusion for Surround ADAS and SuperVision, including Volkswagen programs
leaderJourney 6 B/M/P automotive SoCs power Chinese ADAS programs, including Toyota and Volkswagen-linked deployments
majorHuashan A1000/A2000 driving processors and Wudang cross-domain SoCs supply local perception and vehicle compute
challengerAscend-derived automotive AI and host chips inside MDC platforms run perception and driving workloads
majorR-Car X5H Gen5 combines 3nm central compute and AI acceleration; silicon and evaluation boards are sampling
majorTDA4 is established Jacinto vision compute; TDA5 adds C7 NPUs and chiplet scaling, with first samples due late 2026
majorS32N7 combines application/real-time cores and eIQ Neutron NPU for vehicle-core workloads; S32N79 is sampling
majorCV3-AD central-domain SoCs combine CVflow neural acceleration, perception and sensor fusion for L2+ to L4 designs
challengerExynos Auto V920 integrates a dual-core NPU, Cortex-A78AE and AMD-based Xclipse graphics for intelligent cockpits
challengerDimensity AX C-X1 combines Arm CPU with Nvidia Blackwell GPU and DLA for local cockpit AI
challengerAI4 supplies current FSD silicon; April's AI5 tape-out precedes future production and is not a deployed vehicle generation
majorShenji NX9031 in-house autonomous-driving processor supplies local inference in ET9 and subsequent vehicle programs
challengerTuring in-house AI chip runs automotive perception and driving models, replacing merchant compute in selected designs
challengerMach M100 in-house automotive AI processor debuts in the L9 Livis central driving-compute architecture
challengerRAP1 uses Armv9 Cortex-A720AE and custom neural compute in Gen 3 autonomy hardware targeted for late 2026
emergingXuanji A3 supplies an in-house driving-compute design; May's production announcement does not confirm a vehicle socket
emergingEagle-N automotive accelerator targets 2027 production; Eagle-A integrated ADAS SoC follows on a 2028 roadmap
emergingAD1000/AD800 driving SoCs entered announced mass production in December 2025; SE1000 separately supplies cockpit compute
challengerAURIX TC4x microcontrollers add a parallel-processing unit for vector and AI workloads in vehicle control domains
nicheStellar P3E samples combine Cortex-R52+ control and a Neural-ART NPU for automotive edge inference
emergingJune-launched iND881 edge-AI SoC integrates neural processing for automotive perception and in-cabin monitoring
challengerM57 ADAS SoC powers Aptiv's front-view unit for Europe-bound vehicles; production and deliveries were announced September 16
challenger
Sources: thinkercar.com, prnewswire.com, infineon.com, st.com, investors.indie.inc, developer.nvidia.com
FPGAs & Adaptive Compute
Programmable logic implements inference pipelines and combines custom preprocessing with low-latency control. These companies supply FPGA silicon or tightly integrated programmable processors, spanning large AI engines to small sensor-edge devices.
Versal AI Edge/Gen2 and Zynq adaptive SoCs combine programmable fabric with CPU and AI engines for embedded inference
leaderAgilex 3/5/7 FPGAs integrate AI tensor DSP blocks; FPGA AI Suite maps neural models into programmable fabric
leaderNexus/Nexus 2 and Avant-E FPGAs use sensAI tools for low-power vision, sensor processing and local inference
majorPolarFire SoC combines RISC-V CPUs and FPGA fabric; VectorBlox maps neural inference onto programmable logic
majorSpeedster7t machine-learning blocks, GDDR6 interfaces and 2D NoC accelerate local vision, speech and language inference
challengerTitanium Ti375 integrates Quantum FPGA fabric, hardened RISC-V and memory interfaces for configurable edge compute
challengerEOS S3 combines Cortex-M4F and eFPGA fabric for low-power sensor, voice and TinyML processing
nicheArora V FPGAs add DSP blocks for AI operations; GW5AS variants integrate Arm or RISC-V host cores
challengerSALPHOENIX, SALEAGLE and SALELF FPGA families implement configurable video, industrial and edge-compute pipelines
challengerFPGA and FMQL programmable-SoC families supply Chinese embedded compute and custom inference datapaths
majorLogos, Titan and Kosmo FPGA/SoC families implement programmable vision and industrial acceleration
challengerGateMate A1/A2 FPGAs provide reconfigurable logic and DSP datapaths for embedded compute; A2 became available in July 2026
nicheTX5 chips combine reconfigurable RNE/RCE engines and CGRA image processing; they are programmable processors, not FPGAs
niche
Sources: colognechip.com, tsingmicro.com, altera.com, latticesemi.com, microchip.com, achronix.com
AI Microcontrollers
Microcontrollers and compact fusion processors run neural inference near sensors under tight energy and memory budgets. Some integrate dedicated NPUs; others execute small models with DSP or vector extensions, a distinction stated in each role.
STM32N6 pairs Cortex-M55 with the Neural-ART NPU for real-time camera and audio inference
leaderMCX N and i.MX RT700 use eIQ Neutron NPUs for local neural workloads in control, audio and embedded devices
majorRA8P1 pairs Cortex-M85 with Ethos-U55 for local vision, voice and real-time analytics
majorPSOC Edge E84 pairs Cortex-M55/Ethos-U55 with a low-power M33/NNLite domain for always-on inference
majorMSPM0G5187 ships with TinyEngine NPU; AM13Ex brings the same neural acceleration to real-time control
majorMAX78000/MAX78002 combine Cortex-M4 control and CNN accelerators for battery-powered vision and audio inference
majorApollo510 and July-released Apollo330 Plus/510 Lite use low-power CPUs and Helium processing for local AI
challengerEnsemble E4/E6/E8 combines Cortex cores with Ethos-U55/U85 NPUs; Balletto adds low-power wireless AI
challengernRF54LM20B integrates Axon NPU; Neuton models also run on other nRF54 wireless SoCs without a dedicated NPU
challengerBG24/MG24 and xG26 wireless SoCs integrate AI/ML accelerators for connected sensing and local classification
majorAstra SRW1500 combines Cortex-M52, Ethos-U55 and wireless connectivity for audio and sensing inference
challengerHX6538 WiseEye2 combines Cortex-M55 and Ethos-U55 in an ultralow-power endpoint AI microcontroller
nichedsPIC33AK DSP controllers run compact inference through DSP-ML libraries without requiring a separate NPU
majorESP32-P4 RISC-V AI extensions and ESP-DL run local speech, vision and OCR; this is not a discrete NPU chip
challengerGD32H7 Cortex-M7 MCUs execute DSP-assisted edge models, including voice recognition, without an integrated NPU
nicheEthos-U55/U85 NPU IP and Cortex-M Helium cores underpin neural acceleration inside many vendors' AI MCUs
leaderNeuPro-Nano NPU IP licenses compact always-on inference for smart sensors, audio and battery-powered MCU designs
majorNDP120 and NDP250 Neural Decision Processors run low-power audio, sensor and vision models near the endpoint
challengerM55M1 combines Cortex-M55 Helium and Ethos-U55 inference acceleration for embedded vision and audio
challenger
Sources: nuvoton.com, st.com, renesas.com, infineon.com, ti.com, nordicsemi.com
Sensor-Edge Inference
Smart image and motion sensors, analog neural chips and low-power camera processors extract useful signals near their source. Integrated inference is distinguished from conventional sensing that merely feeds an external AI processor.
IMX500 stacks imaging and AI processing so vision inference runs inside the sensor with local SRAM and DSP
leaderNDP250 processes battery-powered acoustic, vision and motion inputs with its neural decision architecture
majorWiseEye2 pairs HX6538 inference with low-power CMOS sensors for always-on presence and vision sensing
majorSensortec BHI385 smart IMU integrates a programmable processor, motion AI and self-learning sensor software
majorInvenSense SmartMotion ICM-456xx variants combine motion sensing with on-chip fusion and machine-learning capability
majorAkida silicon implements event-based local vision, acoustic and sensor inference; new AKD2500 remains in development
challengerPulsar neuromorphic microcontroller executes low-power spiking-network inference beside sensor inputs
emergingAML100 classifies analog sensor inputs before digitization; RF-focused AML200 is validated test silicon in development
nicheVibroSense analog neural engineering chip taped out in April for tire-friction inference; volume supply is not confirmed
emergingIntelligent MEMS sensors use embedded machine-learning cores to classify motion before waking a host processor
majorAZ3 and AZ3 Pro custom chips perform local wake-word, audio and vision-transformer processing in Echo hardware
majorH2 custom audio silicon performs computational audio and local voice/noise processing in the AirPods family
majorFH8858V500 combines a 1-TOPS engine and AI ISP to process camera images and improve low-light capture locally
challengerGK7205V510 integrates a 1-TOPS NPU with ISP and video encoding for low-power intelligent cameras
challengerT41 uses XBurst2 CPUs and AIE neural acceleration for low-power, always-on video and smart-camera inference
challengeriND880 camera processors feed ADAS perception; the 2026 iND881 adds edge-AI compute for automotive and physical AI
challengerHyperlux image sensors feed ADAS and edge-vision inference pipelines; they do not themselves supply general NPU compute
majorOrion prototype uses custom sensor-processing and AR-acceleration silicon; this is not a mass-market chip launch
emergingOAX4600 moves DMS/OMS inference beside RGB-IR cameras with an integrated NPU; ordinary image sensors remain separate
nicheSPU-001 processes sparse speech and sensor models beside the signal source, reducing host wakeups and memory transfers
niche
Sources: ovt.com, femto.ai, aitrios.sony-semicon.com, bosch-sensortec.com, tdk-electronics.tdk.com, aspinity.com
Glossary
- NPU
- A neural processing unit accelerates operations used in neural-network inference.
- SoC
- A system on chip integrates processors, memory interfaces and peripheral functions on one device.
- FPGA
- A field-programmable gate array can be reconfigured after manufacturing to implement custom compute pipelines.
- MCU
- A microcontroller combines a compact CPU, memory and peripherals for embedded control and small inference workloads.
- TOPS
- Trillions of operations per second; precision, sparsity and utilization must match for meaningful comparisons.
- ISP
- An image signal processor converts raw sensor data into usable images before or alongside vision inference.
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