Synopsys (SNPS)
Design software, silicon IP, and multiphysics simulation for chips and complex products.
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Synopsys supplies the digital workbenches used to design chips, and its purchase of Ansys has made it a much broader seller of engineering simulation. Chip design still brings in most of the money; the next chapter is joining those tools so engineers can test heat, motion and electricity before building anything physical.
Item facts: 9M FY2026 · nine months ended Jul 31, 2026, from filings, earnings calls and company pages.
Judgment weights, not filed revenue
The band summarizes business focus and direction. ~ marks estimates.
7 in detail · 12 more below
EDA
The main chip-design workbench and Synopsys’ largest business. Companywide customer commitments stretch several years ahead; watch whether increasingly complex chips keep demand strong while export restrictions weigh on China.
Competes with Digital Full Flow (Cadence) · Calibre Design and Verification (Siemens EDA)
In plain English
Before a new chip reaches a factory, engineers need to draw it, check that every connection works and prove that the finished design can actually be made. EDA is Synopsys’ collection of digital workbenches for those jobs, from the first sketch through the final factory checks.
Chip makers, cloud companies and chip factories usually sign two- or three-year agreements for the software and its updates. Changing workbenches halfway through a design is risky and expensive, so customers tend to stay. New chip complexity creates more checking work; export permissions and customers’ research budgets can still slow new projects.
Design IP
Pre-tested chip building blocks that save customers from starting at zero. This line is 18.6% of current revenue; watch delivery timing, China restrictions and whether customer designs reach chip production.
Competes with Protocol IP (Cadence) · Interface and Security IP (Rambus)
In plain English
Think of this as a shelf of pre-tested parts for a chip. A customer can license a ready-made memory connection, security unit or other building block instead of designing every piece alone, then fit it into a larger design.
Synopsys gets paid when it hands over the block, for custom work that adapts it, and sometimes again when the customer sells finished chips. That makes the timing bumpier than a steady software subscription. The business depends on keeping each block compatible with new technical standards and chip factories, then on customers carrying their designs all the way into production.
ZeBu and HAPS
Dedicated machines let teams run a large chip design before the real chip exists. Sales are not separated from EDA; component availability and delivery dates make this business lumpier and less profitable than software alone.
Competes with Palladium and Protium (Cadence) · Veloce Strato CS (Siemens EDA)
In plain English
A chip can take years to build, but the software meant to run on it cannot wait that long. ZeBu and HAPS are rehearsal machines: they imitate the unfinished chip quickly enough for engineers to find mistakes and begin testing software before the real part comes back from a factory.
Customers either buy or lease the machines and then pay for upkeep. Synopsys earns a larger payment when equipment arrives, followed by steadier support money. Unlike a downloaded program, this business needs physical components on time, so supply shortages or a delayed shipment can move sales from one quarter to another.
3DIC Compiler
A planning and checking system for chips assembled from several pieces. Sales stay inside EDA; watch whether hotter, more crowded AI designs make this joined-up packaging work a routine part of projects.
Competes with Integrity 3D-IC (Cadence) · Innovator3D IC (Siemens EDA)
In plain English
Instead of squeezing an entire advanced chip onto one flat piece, engineers can place several smaller pieces together in a package. 3DIC Compiler is the planner for that crowded little neighborhood: it decides where pieces sit, how they connect and whether the complete arrangement can be built and checked.
Customers access it through broader chip-design agreements. Synopsys can also attach Ansys tools that test heat, electrical behavior and physical stress, making the combined package harder to replace with separate programs. Accurate factory instructions, connection standards and heat models are what make the plan trustworthy enough to manufacture.
Synopsys.ai
Automated helpers search through design choices and perform repeatable engineering tasks. Revenue is folded into existing tools or extra usage; watch whether customers trust the output enough to let these helpers handle production work.
Competes with Cerebrus AI Studio (Cadence) · ChipAgents platform (ChipAgents)
In plain English
Searching millions of possible chip layouts by hand is slow. Synopsys.ai gives the design tools an automated helper that can try options, compare the results and take on sequences of routine work, while engineers check what it produces.
There is no separate sales line for it. Customers pay through their existing software agreements or by using more tool time, including hosted computing from Synopsys. The opportunity is to make each engineer more productive and deepen use of the wider toolkit. The brake is trust: protected design files must stay safe, and every automated answer must be reliable enough for an expensive chip project.
Ansys
Computer testing for products that must survive heat, motion, fluids and electricity. Ansys already supplies 31.4% of current revenue; watch renewals and whether Synopsys can sell these tools beyond their existing engineering users.
Competes with SIMULIA Abaqus (Dassault Systèmes) · COMSOL Multiphysics (COMSOL) · Simcenter (Siemens)
In plain English
Ansys lets an engineer crash, heat, bend or blow air across a product on a computer before anyone builds the costly physical version. Carmakers can test a body panel, aircraft teams can study airflow, and electronics makers can see whether a device will overheat.
Companies pay for time-limited access, buy lasting licenses with ongoing upkeep, or hire specialists for help. They keep paying because every new product brings another round of safety and performance questions. Bought in July 2025, Ansys is the piece that turned Synopsys from mainly a chip-design supplier into a broader engineering-software company.
Multiphysics Fusion
The first combined products connect chip design directly with tests for heat, power and other physical effects. They arrived in June 2026 and add little this year; adoption next year is the first real proof point.
Competes with Integrity 3D-IC with analysis tools (Cadence) · Innovator3D IC and Simcenter (Siemens)
In plain English
This is the bridge Synopsys bought Ansys to build. A chip designer can change a layout and immediately check how the same change affects heat, electrical behavior or physical stress, without carrying files between disconnected programs. The first four combined paths became available in June 2026.
Synopsys plans to sell them as additions to relationships it already has on both sides. That creates a simple route to money: persuade chip-design customers to buy more simulation, and simulation customers to use more Synopsys design tools. Cisco Silicon One, MediaTek, NVIDIA and Samsung Foundry helped test or confirm the first releases, but this year’s sales contribution is small.
EDAThe main chip-design workbench and Synopsys’ largest business. Companywide customer commitments stretch several years ahead; watch whether increasingly complex chips keep demand strong while export restrictions weigh on China.The main chip-design workbench and Synopsys’ largest business. Companywide customer commitments stretch several years ahead; watch whether increasingly complex chips keep demand strong while export restrictions weigh on China.
In plain English
Before a new chip reaches a factory, engineers need to draw it, check that every connection works and prove that the finished design can actually be made. EDA is Synopsys’ collection of digital workbenches for those jobs, from the first sketch through the final factory checks.
Chip makers, cloud companies and chip factories usually sign two- or three-year agreements for the software and its updates. Changing workbenches halfway through a design is risky and expensive, so customers tend to stay. New chip complexity creates more checking work; export permissions and customers’ research budgets can still slow new projects.
Competes with Digital Full Flow (Cadence) · Calibre Design and Verification (Siemens EDA)
Design IPPre-tested chip building blocks that save customers from starting at zero. This line is 18.6% of current revenue; watch delivery timing, China restrictions and whether customer designs reach chip production.Pre-tested chip building blocks that save customers from starting at zero. This line is 18.6% of current revenue; watch delivery timing, China restrictions and whether customer designs reach chip production.
In plain English
Think of this as a shelf of pre-tested parts for a chip. A customer can license a ready-made memory connection, security unit or other building block instead of designing every piece alone, then fit it into a larger design.
Synopsys gets paid when it hands over the block, for custom work that adapts it, and sometimes again when the customer sells finished chips. That makes the timing bumpier than a steady software subscription. The business depends on keeping each block compatible with new technical standards and chip factories, then on customers carrying their designs all the way into production.
Competes with Protocol IP (Cadence) · Interface and Security IP (Rambus)
ZeBu and HAPSDedicated machines let teams run a large chip design before the real chip exists. Sales are not separated from EDA; component availability and delivery dates make this business lumpier and less profitable than software alone.Dedicated machines let teams run a large chip design before the real chip exists. Sales are not separated from EDA; component availability and delivery dates make this business lumpier and less profitable than software alone.
In plain English
A chip can take years to build, but the software meant to run on it cannot wait that long. ZeBu and HAPS are rehearsal machines: they imitate the unfinished chip quickly enough for engineers to find mistakes and begin testing software before the real part comes back from a factory.
Customers either buy or lease the machines and then pay for upkeep. Synopsys earns a larger payment when equipment arrives, followed by steadier support money. Unlike a downloaded program, this business needs physical components on time, so supply shortages or a delayed shipment can move sales from one quarter to another.
Competes with Palladium and Protium (Cadence) · Veloce Strato CS (Siemens EDA)
3DIC CompilerA planning and checking system for chips assembled from several pieces. Sales stay inside EDA; watch whether hotter, more crowded AI designs make this joined-up packaging work a routine part of projects.A planning and checking system for chips assembled from several pieces. Sales stay inside EDA; watch whether hotter, more crowded AI designs make this joined-up packaging work a routine part of projects.
In plain English
Instead of squeezing an entire advanced chip onto one flat piece, engineers can place several smaller pieces together in a package. 3DIC Compiler is the planner for that crowded little neighborhood: it decides where pieces sit, how they connect and whether the complete arrangement can be built and checked.
Customers access it through broader chip-design agreements. Synopsys can also attach Ansys tools that test heat, electrical behavior and physical stress, making the combined package harder to replace with separate programs. Accurate factory instructions, connection standards and heat models are what make the plan trustworthy enough to manufacture.
Competes with Integrity 3D-IC (Cadence) · Innovator3D IC (Siemens EDA)
Synopsys.aiAutomated helpers search through design choices and perform repeatable engineering tasks. Revenue is folded into existing tools or extra usage; watch whether customers trust the output enough to let these helpers handle production work.Automated helpers search through design choices and perform repeatable engineering tasks. Revenue is folded into existing tools or extra usage; watch whether customers trust the output enough to let these helpers handle production work.
In plain English
Searching millions of possible chip layouts by hand is slow. Synopsys.ai gives the design tools an automated helper that can try options, compare the results and take on sequences of routine work, while engineers check what it produces.
There is no separate sales line for it. Customers pay through their existing software agreements or by using more tool time, including hosted computing from Synopsys. The opportunity is to make each engineer more productive and deepen use of the wider toolkit. The brake is trust: protected design files must stay safe, and every automated answer must be reliable enough for an expensive chip project.
Competes with Cerebrus AI Studio (Cadence) · ChipAgents platform (ChipAgents)
AnsysComputer testing for products that must survive heat, motion, fluids and electricity. Ansys already supplies 31.4% of current revenue; watch renewals and whether Synopsys can sell these tools beyond their existing engineering users.Computer testing for products that must survive heat, motion, fluids and electricity. Ansys already supplies 31.4% of current revenue; watch renewals and whether Synopsys can sell these tools beyond their existing engineering users.
In plain English
Ansys lets an engineer crash, heat, bend or blow air across a product on a computer before anyone builds the costly physical version. Carmakers can test a body panel, aircraft teams can study airflow, and electronics makers can see whether a device will overheat.
Companies pay for time-limited access, buy lasting licenses with ongoing upkeep, or hire specialists for help. They keep paying because every new product brings another round of safety and performance questions. Bought in July 2025, Ansys is the piece that turned Synopsys from mainly a chip-design supplier into a broader engineering-software company.
Competes with SIMULIA Abaqus (Dassault Systèmes) · COMSOL Multiphysics (COMSOL) · Simcenter (Siemens)
Multiphysics FusionThe first combined products connect chip design directly with tests for heat, power and other physical effects. They arrived in June 2026 and add little this year; adoption next year is the first real proof point.The first combined products connect chip design directly with tests for heat, power and other physical effects. They arrived in June 2026 and add little this year; adoption next year is the first real proof point.
In plain English
This is the bridge Synopsys bought Ansys to build. A chip designer can change a layout and immediately check how the same change affects heat, electrical behavior or physical stress, without carrying files between disconnected programs. The first four combined paths became available in June 2026.
Synopsys plans to sell them as additions to relationships it already has on both sides. That creates a simple route to money: persuade chip-design customers to buy more simulation, and simulation customers to use more Synopsys design tools. Cisco Silicon One, MediaTek, NVIDIA and Samsung Foundry helped test or confirm the first releases, but this year’s sales contribution is small.
Competes with Integrity 3D-IC with analysis tools (Cadence) · Innovator3D IC and Simcenter (Siemens)
Named in filings, launches and programs
- Custom Design FamilyProduct lineTools for drawing and checking custom and analog chips, where engineers shape circuits by hand rather than rely mainly on automation.
- Manufacturing SolutionsProduct lineSoftware for modeling how chips are made, preparing factory patterns and finding production problems that reduce the number of usable chips.
- Silicon Lifecycle ManagementPlatformMonitors chips from factory testing through everyday use, helping customers spot failures and improve later production runs.
- SynplifyProduct lineTurns a design into instructions for a reprogrammable chip, serving teams that need flexible hardware rather than a fixed custom chip.
- Synopsys CloudPlatformHosted access to design tools and extra computing power; more than one hundred startups were using the service in production.
- IP AcceleratedServiceHands-on help fitting Synopsys’ ready-made chip blocks into a customer’s design and getting that design ready for production.
- Other product groupProduct lineUniversity programs, machinery simulation and currency-contract effects together supply the remaining 0.5% of current revenue.
- NVIDIA Strategic PartnershipCustomer programA non-exclusive engineering partnership around faster simulation, automated design and virtual product copies; NVIDIA’s investment is financing, not customer sales.
- Full-flow AI-customer commitmentCustomer programAn unnamed artificial-intelligence customer made a multi-year commitment to use the full set of digital chip-design tools.
- GPU-accelerated CFD digital-twin programCustomer programAn unnamed electronics maker chose faster fluid-flow simulation for a company-wide virtual copy of a physical system, becoming the quarter’s largest Ansys deal.
- AWS Graviton 5 enablementCustomer programAmazon’s cloud-chip team used several Synopsys tools to design, check timing and inspect the factory-ready Graviton 5 design.
- AMD/Microsoft autonomous EDA workflowsCustomer program · RampingAMD and Microsoft are testing automated chip-design sequences aimed at real production work, not just question-and-answer assistance.
Custom Design FamilyProduct line
Tools for drawing and checking custom and analog chips, where engineers shape circuits by hand rather than rely mainly on automation.
Manufacturing SolutionsProduct line
Software for modeling how chips are made, preparing factory patterns and finding production problems that reduce the number of usable chips.
Silicon Lifecycle ManagementPlatform
Monitors chips from factory testing through everyday use, helping customers spot failures and improve later production runs.
SynplifyProduct line
Turns a design into instructions for a reprogrammable chip, serving teams that need flexible hardware rather than a fixed custom chip.
Synopsys CloudPlatform
Hosted access to design tools and extra computing power; more than one hundred startups were using the service in production.
IP AcceleratedService
Hands-on help fitting Synopsys’ ready-made chip blocks into a customer’s design and getting that design ready for production.
Other product groupProduct line
University programs, machinery simulation and currency-contract effects together supply the remaining 0.5% of current revenue.
NVIDIA Strategic PartnershipCustomer program
A non-exclusive engineering partnership around faster simulation, automated design and virtual product copies; NVIDIA’s investment is financing, not customer sales.
Full-flow AI-customer commitmentCustomer program
An unnamed artificial-intelligence customer made a multi-year commitment to use the full set of digital chip-design tools.
GPU-accelerated CFD digital-twin programCustomer program
An unnamed electronics maker chose faster fluid-flow simulation for a company-wide virtual copy of a physical system, becoming the quarter’s largest Ansys deal.
AWS Graviton 5 enablementCustomer program
Amazon’s cloud-chip team used several Synopsys tools to design, check timing and inspect the factory-ready Graviton 5 design.
AMD/Microsoft autonomous EDA workflowsCustomer program · Ramping
AMD and Microsoft are testing automated chip-design sequences aimed at real production work, not just question-and-answer assistance.